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8-channel, 10- and 12-bit adcs with i 2 c- compatible interface in 20-lead tssop ad7997/ad7998 rev. 0 in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . s p ecificatio n s subj ec t to ch an g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 326. 87 03 ? 2004 analog de vices, i n c. al l r i ght s r e ser v ed . features 10- an d 12 -bit adc with fast c o nversion time: 2 s typ 8 single-en ded analog input channels specified for v dd of 2.7 v to 5. 5 v low power con s umption fast throughput rate: up to 1 88 ksps sequencer ope r ation au tomatic cy cle mode i 2 c?-compatibl e serial interfac e supports stan dard, f a st, and high spee d mo des out-of-range i n dicator/alert f u nction pin-selectable addressing via as shutdown mode: 1 a max temperature r a nge: ? 40c to +85 c 20-lea d tssop package see the ad79 9 2 and ad7 994 f o r 2-channel a n d 4-channel equ i valent d e vices, respectiv e ly general de scription the ad7997/ad7998 a r e 8-c h a nne l , 10- and 1 2 -b i t , lo w p o w e r , successi v e a p p r o x ima t ion ad c s w i t h an i 2 c-com p a t i b le in t e r f ace . the p a r t s o p era t e f r om a sin g l e 2.7 v t o 5.5 v p o w e r su p p ly a nd fe a t ur e a 2 s co n v e r sio n t i me. t h e p a r t s co n t a i n an 8 - ch an nel m u lt ipl e xe r and t r a c k - a n d - hol d am pl i f i e r t h a t c a n ha nd le in p u t f r e q uen c ies u p t o 11 mh z. the ad7997/ad7998 p r o v ide a 2-wir e s e r i al in t e r f ace tha t is co m p a t i b le wi th i 2 c in t e r f aces. e a ch p a r t co m e s in t w o v e rsio n s , ad7997-0 / ad7 998-0 a nd ad7 997-1/ad7998-1, a n d e a c h v e rsio n a l lo ws a t le ast tw o dif f er en t i 2 c addr es s e s. th e i 2 c in t e r f ace on t h e ad7997-0 / ad7 998-0 s u p p o r ts s t anda r d and fas t i 2 c i n t e r f ac e m o des. th e i 2 c in ter f ace o n t h e ad7997 -1/ ad7998-1 su p p o r ts s t a n da r d , fas t , an d hig h sp e e d i 2 c in t e r f ace mo d e s . the ad7997/ad7998 n o r m al ly r e ma in in a sh u t do wn s t a t e w h i l e not c o n v e r t i ng , an d p o we r up on ly for c o n v e r s i ons . t h e co n v ersio n p r o c es s can b e co n t rol l e d usin g t h e co n v s t pi n , b y a co mmand m o de w h er e con v ersio n s o c c u r acr o s s i 2 c wr i t e op e r a t i o n s or an a u tom a t i c c o n v e r s i on i n t e r v a l mo d e s e l e c t e d t h rou g h s o f t w a re c o n t ro l. the ad7997/ad7998 r e q u ir e an ext e r n al r e f e r e n c e tha t sh o u ld be a p p l i e d t o t h e r e f in p i n an d ca n b e in t h e r a n g e o f 1.2 v to v dd . this a l lo ws t h e wide st d y n a mic in p u t ra n g e t o t h e ad c. function al block di ag ram v in 1 10-/12-bit successive approximation adc control logic 8:1 i/p mux ad7997/ad7998 v dd scl i 2 c interface cycle timer register alert status register configuration register conversion result register sda agnd alert/busy convst agnd as oscillator ref in v in 8 data low limit re g i s t e r ch 1 ? ch4 t/h data high limit re g i s t e r ch 1 ? ch4 hysteresis re g i s t e r ch1 ? c h 4 03473- 0- 001 fi g u r e 1 . o n - c hi p l i mi t r e gi s t e r s c a n be p r ogra m m ed wi th h i gh a n d l o w l i m i t s f o r t h e c o n v e r s i o n re s u lt , an d a n op e n - d r a i n , out - of - ra n g e in d i ca t o r o u t p u t (aler t ) beco m e s active w h en t h e p r og ra mm e d hig h o r lo w limi ts a r e viol a t e d b y t h e con v ersio n r e s u l t . this o u t p u t can b e us ed as a n in t e r r u p t. produc t h i ghligh ts 1. 2 s co n v ersio n t i me wi t h lo w p o w e r co n s um p t i o n. 2. i 2 c-co m p a t i b le s e r i al in t e r f ace wi t h p i n-s e le c t ab le addr es s e s. t w o ad7997/ad79 98 v e rsio n s al lo w f i v e ad7997/ad79 98 de vices t o be co nnec t e d t o the s a m e se ri al b u s . 3. the p a r t s fe a t ure a u t o ma t i c s h ut do w n w h i l e n o t co n v er t i ng t o max i m i z e p o w e r ef f i c i e n c y . c u r r en t con s u m pt ion is 1 a max w h en i n sh u t do w n m o de a t 3v . 4. refer e nce can b e dr i v en u p to t h e p o w e r su p p ly . 5. o u t-o f -r a n ge i ndic a to r t h a t can b e s o f t wa r e dis a b l e d o r ena b le d. 6. on e - sh o t and a u t o ma t i c con v e r sio n ra t e s. 7. reg i sters sto r e mini m u m an d max i m u m con v ersio n re su lt s .
ad7997/ad7998 rev. 0 | page 2 of 32 table of contents ad7997 specifications ..................................................................... 3 ad7998 specifications ..................................................................... 5 i 2 c timing specifications ................................................................ 7 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and pin function descriptions .................... 10 te r m i no l o g y .................................................................................... 11 typical performance characteristics ........................................... 12 circuit information ........................................................................ 15 converter operation .................................................................. 15 typical connection diagram ................................................... 16 analog input ............................................................................... 16 internal register structure ............................................................ 18 address pointer register ........................................................... 18 configuration register .............................................................. 19 conversion result register ....................................................... 20 limit registers ............................................................................ 20 alert status register (ch1 to ch4) ........................................ 21 cycle timer register .................................................................. 22 sample delay and bit trial delay ............................................. 22 serial interface ................................................................................ 23 serial bus address ...................................................................... 23 writing to the ad7997/ad7998 .................................................. 24 writing to the address pointer register for a subsequent read .............................................................................................. 24 writing a single byte of data to the alert status register or cycle register .............................................................................. 24 writing two bytes of data to a limit, hysteresis, or configuration register .............................................................. 24 reading data from the ad7997/ad7998 ................................... 26 alert/busy pin .......................................................................... 27 smbus alert ............................................................................ 27 busy ............................................................................................ 27 placing the ad7997-1/ad7998-1 into high speed mode ... 27 the address select (as) pin ..................................................... 27 modes of operation ....................................................................... 28 mode 1using the convst pin ........................................... 28 mode 2 C command mode ............................................... 29 mode 3automatic cycle interval mode .............................. 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 related parts in i 2 c-compatible adc product family ........ 31 revision history 9/04revision 0: initial version
ad7997/ad7998 rev. 0 | page 3 of 32 ad7997 specifications temperature range for b version is ?40c to +85c. unless otherwise noted, v dd = 2.7 v to 5.5 v; ref in = 2.5 v; for the ad7997-0, all specifications apply for f scl up to 400 khz; for the ad7997-1, all specifications apply for f scl up to 3.4 mhz, unless otherwise noted; t a = t min to t max . table 1. parameter b version unit test conditions/comments dynamic performance 1 f in = 10 khz sine wave for f scl from 1.7 mhz to 3.4 mhz f in = 1 khz sine wave for f scl up to 400 khz signal to noise + distortion (sinad) 2 61 db min total harmonic distortion (thd) 2 C75 db max peak harmonic or spurious noise (sfdr) 2 C76 db max intermodulation distortion (imd) 2 fa = 10.1 khz, fb = 9.9 khz for f scl from 1.7 mhz to 3.4 mhz fa = 1.1 khz, fb = 0.9 khz for f scl up to 400 khz second-order terms C86 db typ third-order terms C86 db typ aperture delay 2 10 ns max aperture jitter 2 50 ps typ channel-to-channel isolation 2 C90 db typ f in = 108 hz, see the terminology section full-power bandwidth 2 11 mhz typ @ 3 db 2 mhz typ @ 0.1 db dc accuracy resolution 10 bits integral nonlinearity 1, 2 0.5 lsb max differential nonlinearity 1, 2 0.5 lsb max guaranteed no missed codes to 10 bits offset error 2 1.5 lsb max mode 1 ( convst mode) 2.5 lsb max mode 2 (command mode) offset error match 2 0.5 lsb max gain error 2 1.5 lsb max gain error match 2 0.5 lsb max analog input input voltage range 0 to ref in v dc leakage current 1 a max input capacitance 30 pf typ reference input ref in input voltage range 1.2 to v dd v min/v max dc leakage current 1 a max input impedance 69 k? typ during a conversion logic inputs (sda, scl) input high voltage, v inh 0.7 (v dd ) v min input low voltage, v inl 0.3 (v dd ) v max input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 3 10 pf max input hysteresis, v hyst 0.1 (v dd ) v min
ad7997/ad7998 rev. 0 | page 4 of 32 parameter b version unit test conditions/comments logic inputs ( convst ) input high voltage, v inh 2.4 v min v dd = 5 v 2.0 v min v dd = 3 v input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 3 10 pf max logic outputs (open-drain) output low voltage, v ol 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma floating-state leakage current 1 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary conversion rate see the modes of operation section conversion time 2 s typ throughput rate mode 1 (reading after the conversion) 5 ksps typ f scl = 100 khz 21 ksps typ f scl = 400 khz 121 ksps typ f scl = 3.4 mhz mode 2 5.5 ksps typ f scl = 100 khz 22 ksps typ f scl = 400 khz 147 ksps typ f scl = 3.4 mhz, 188 ksps typ @ 5 v power requirements v dd 2.7/5.5 v min/max i dd digital inputs = 0 v or v dd power-down mode, interface inactive 1/2 a max v dd = 3.3 v/5.5 v power-down mode, interface active 0.07/0.3 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.3/0.6 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl operating, interface inactive 0.06/0.1 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.3/0.6 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl operating, interface active 0.15/0.4 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.6/1.1 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 1 0.7/1.4 ma typ v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 2 mode 3 (i 2 c inactive, t convert x 32) 0.7/1.5 ma max v dd = 3.3 v/5.5 v power dissipation fully operational operating, interface active 0.495/2.2 mw max v dd = 3.3 v/5.5 v, 400 khz f scl 1.98/6.05 mw max v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 1 2.31/7.7 mw typ v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 2 power down, interface inactive 3.3/11 w max v dd = 3.3 v/5.5 v 1 max/min ac dynamic performance, inl and dnl specifications are typical specificat ions when operating in mode 2 with i 2 c hs-mode scl frequenc ies. specifications outlined for mode 2 apply to mode 3 also. sample delay and bit trial delay enabled. 2 see the terminology section. 3 guaranteed by initial characterization.
ad7997/ad7998 rev. 0 | page 5 of 32 ad7998 specifications temperature range for b version is ?40c to +85c. unless otherwise noted, v dd = 2.7 v to 5.5 v; ref in = 2.5 v; for the ad7998-0, all specifications apply for f scl up to 400 khz; for the ad7998-1, all specifications apply for f scl up to 3.4 mhz, unless otherwise noted; t a = t min to t max . table 2. parameter b version unit test conditions/comments dynamic performance 1 f in = 10 khz sine wave for f scl from 1.7 mhz to 3.4 mhz f in = 1 khz sine wave for f scl up to 400 khz signal-to-noise + distortion (sinad) 2 70.5 db min signal to noise ratio (snr) 2 71 db min total harmonic distortion (thd) 2 C78 db max peak harmonic or spurious noise (sfdr) 2 C79 db max intermodulation distortion (imd) 2 fa = 10.1 khz, fb = 9.9 khz f scl from 1.7 mhz to 3.4 mhz fa = 1.1 khz, fb = 0.9 khz for f scl up to 400 khz second-order terms C90 db typ third-order terms C90 db typ aperture delay 2 10 ns max aperture jitter 2 50 ps typ channel-to-channel isolation 2 C90 db typ f in = 108 hz, see the terminology section full-power bandwidth 2 11 mhz typ @ 3 db 2 mhz typ @ 0.1 db dc accuracy resolution 12 bits integral nonlinearity 1,2 1 lsb max 0.2 lsb typ differential nonlinearity 1,2 +1/C0.9 lsb max guaranteed no missed codes to 12 bits 0.2 lsb typ offset error 2 4 lsb max mode 1 ( convst mode) 6 lsb max mode 2 (command mode) offset error match 2 1 lsb max gain error 2 2 lsb max gain error match 2 1 lsb max analog input input voltage range 0 to ref in v dc leakage current 1 a max input capacitance 30 pf typ reference input ref in input voltage range 1.2 to v dd v min/v max dc leakage current 1 a max input impedance 69 k? typ logic inputs (sda, scl) input high voltage, v inh 0.7 (v dd ) v min input low voltage, v inl 0.3 (v dd ) v max input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 3 10 pf max input hysteresis, v hyst 0.1 (v dd ) v min
ad7997/ad7998 rev. 0 | page 6 of 32 parameter b version unit test conditions/comments logic inputs ( convst ) input high voltage, v inh 2.4 v min v dd = 5 v 2.0 v min v dd = 3 v input low voltage, v inl 0.8 v max v dd = 5 v 0.4 v max v dd = 3 v input leakage current, i in 1 a max v in = 0 v or v dd input capacitance, c in 3 10 pf max logic outputs (open-drain) output low voltage, v ol 0.4 v max i sink = 3 ma 0.6 v max i sink = 6 ma floating-state leakage current 1 a max floating-state output capacitance 3 10 pf max output coding straight (natural) binary conversion rate see the modes of operation section conversion time 2 s typ throughput rate mode 1 (reading after the conversion) 5 ksps typ f scl = 100 khz 21 ksps typ f scl = 400 khz 121 ksps typ f scl = 3.4 mhz mode 2 5.5 ksps typ f scl = 100 khz 22 ksps typ f scl = 400 khz 147 ksps typ f scl = 3.4 mhz , 188 ksps typ @ 5 v power requirements v dd 2.7/5.5 v min/max i dd digital inputs = 0 v or v dd power-down mode, interface inactive 1/2 a max v dd = 3.3 v/5.5 v power-down mode, interface active 0.07/0.3 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.3/0.6 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl operating, interface inactive 0.06/0.1 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.3/0.6 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl operating, interface active 0.15/0.4 ma max v dd = 3.3 v/5.5 v, 400 khz f scl 0.6/1.1 ma max v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 1 0.7/1.4 ma typ v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 2 mode 3 (i 2 c inactive, t convert x 32) 0.7/1.5 ma max v dd = 3.3 v/5.5 v power dissipation fully operational operating, interface active 0.495/2.2 mw max v dd = 3.3 v/5.5 v, 400 khz f scl 1.98/6.05 mw max v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 1 2.31/7.7 mw typ v dd = 3.3 v/5.5 v, 3.4 mhz f scl mode 2 power down, interface inactive 3.3/11 w max v dd = 3.3 v/5.5 v 1 max/min ac dynamic performance, inl and dnl specifications are typical specificat ions when operating in mode 2 with i 2 c hs-mode scl frequenc ies. specifications outlined for mode 2 apply to mode 3 also. sample delay and bit trial delay enabled. 2 see the section. terminology 3 guaranteed by initial characterization.
ad7997/ad7998 rev. 0 | page 7 of 32 i 2 c timing specifications guaranteed by initial characterization. all values measured with input filtering enabled. c b refers to capacitive load on the bus line. t r and t f measured between 0.3 vdd and 0.7 vdd. high speed mode timing specifications apply to the ad7997-1/ad7998-1 only. standard and fast mode timing specifications apply t o both the ad7997-0/ad7998-0 and the ad7997-1/ad7998-1. see figure 2. unless otherwise noted, v dd = 2.7 v to 5.5 v; ref in = 2.5 v; t a =t min to t max . table 3. ad7997/ad7998 limit at t min , t max parameter conditions min max unit description f scl standard mode 100 khz serial clock frequency fast mode 400 khz high speed mode c b = 100 pf max 3.4 mhz c b = 400 pf max 1.7 mhz t 1 standard mode 4 s t high , scl high time fast mode 0.6 s high speed mode c b = 100 pf max 60 ns c b = 400 pf max 120 ns t 2 standard mode 4.7 s t low , scl low time fast mode 1.3 s high speed mode c b = 100 pf max 160 ns c b = 400 pf max 320 ns t 3 standard mode 250 ns t su;dat , data setup time fast mode 100 ns high speed mode 10 ns t 4 1 standard mode 0 3.45 s t hd;dat , data hold time fast mode 0 0.9 s high speed mode c b = 100 pf max 0 70 2 ns c b = 400 pf max 0 150 ns t 5 standard mode 4.7 s t su;sta , setup time for a repeated start condition fast mode 0.6 s high speed mode 160 ns t 6 standard mode 4 s t hd;sta , hold time (repeated) start condition fast mode 0.6 s high speed mode 160 ns t 7 standard mode 4.7 s t buf , bus free time between a stop and a start condition fast mode 1.3 s t 8 standard mode 4 s t su;sto , setup time for stop condition fast mode 0.6 s high speed mode 160 ns t 9 standard mode 1000 ns t rda , rise time of sda signal fast mode 20 + 0.1 c b 300 ns high speed mode c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns
ad7997/ad7998 rev. 0 | page 8 of 3 2 ad79 97/a d 79 9 8 l i mit at t mi n , t max param e t e r c o n d i t i o n s m i n m a x u n i t descr i p t i o n t 10 standard mode 300 ns t fda , f a ll tim e of sda sig na l fast mode 20 + 0.1 c b 300 ns high speed mod e c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns t 11 standard mode 1000 ns t rc l , rise time o f scl signal fast mode 20 + 0.1 c b 300 ns high speed mod e c b = 100 pf max 10 40 ns c b = 400 pf max 20 80 ns t 11a standard mode 1000 ns t rc l 1 , rise time of scl signal after a repeated start c o ndition and after an ac know l e dge bit fast mode 20 + 0.1 c b 300 ns high speed mod e c b = 100 pf max 10 80 ns c b = 400 pf max 20 160 ns t 12 standard mode 300 ns t fcl , f a ll tim e of sc l sig na l fast mode 20 + 0.1 c b 300 ns high speed mod e c b = 100 pf max 10 40 ns c b = 400 pf max 20 80 ns t sp fast mode 0 50 ns pulse width of su ppressed spike high speed mod e 0 10 ns t power - u p 1 typ s po wer-up time 1 a devi ce m u st pr o v i d e a da t a h o ld t i m e f o r sd a i n ord e r t o bri d g e t h e un de fi n e d r e gi on of t h e scl fa l l i n g e d ge. 2 for 3 v supp li es, t h e maximum hol d time with c b = 100 p f max is 100 ns ma x. p s s p t 6 t 4 t 1 t 3 t 5 t 8 t 2 t 11 t 12 t 6 scl sda t 7 t 9 t 10 s = start condition p = stop condition 03473-0-002 f i gure 2. ti ming d i agr a m f o r 2-w i r e s e ri al inter f ace
ad7997/ad7998 rev. 0 | page 9 of 3 2 absolute maximum ra tings t a = 2 5 c , u n l e ss ot he r w i s e not e d. table 4. p a r a m e t e r r a t i n g v dd to gnd ?0.3 v to 7 v analog input voltage to gnd ?0.3 v to v dd + 0.3 v reference input voltage to gnd ?0.3 v to v dd + 0.3 v digital input voltage to gnd ?0.3 v to +7 v digital output v o ltage to gnd ?0.3 v to v dd + 0.3 v input current to any pin except supplies 1 10 ma operating tem p erature range commercia l (b version) ?40c to +85c storage temperature range ?65c to +150 junction tempe r ature 150c 20-lead tssop ja thermal impedance 143c/w jc thermal imp e dance 45c/w pb/sn tempera ture, soldering reflow (10 s to 30 s) 240 (+0/-5)c pb-free temperature, soldering r e f l o w 2 6 0 ( + 0 ) c e s d 1 . 5 k v 1 t r ansien t cur r en ts of up t o 100 m a do not cause scr la t c h-up . s t r e s s es a b o v e t h os e lis t e d u n de r a b s o l u t e m a xi m u m r a t i n g s ma y c a us e p e r m a n en t dama ge t o t h e de vice . this is a s t r e s s r a t i ng o n ly ; f u nc t i on a l op e r a t i o n of t h e d e v i c e a t t h e s e or a n y o t h e r con d i t io ns a b o v e t h os e list e d i n t h e o p era t io nal s e c t io n s o f t h is sp e c if ic a t io n is n o t i m pli e d . e x p o sur e t o a b s o l u t e max i m u m ra t i ng co ndi t i on s fo r ex ten d e d p e r i o d s ma y a f fe c t de vice r e l i ab i l i t y . esd c a ution esd (electrostatic discharge) sensitive device. ele c tros tatic charg e s as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge wi thout detection. although this product features proprietary esd protection circu i try, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. theref ore, prop er esd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad7997/ad7998 rev. 0 | page 10 of 32 pin conf igura t ion and pi n function descriptions ad7997/ ad7998 top view 1 2 3 4 17 18 19 20 sda scl v dd agnd v in 4 14 13 v in 2 5 (not to scale) alert/busy 16 v dd 15 as agnd ref in 6 v in 1 7 v in 3 8 agnd agnd v in 5 9 v in 7 10 v in 8 12 11 v in 6 03473-0-003 convst f i g u re 3. a d 79 98 /a d79 9 7 pin conf ig u r at i o n ta ble 5. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic function 1, 3, 4, 20 agnd analog grou nd. ground referenc e point for all circ uitr y on the a d 7 997/ ad 799 8. all analog input sig nals shou ld be referred to this agnd vol t age. 2, 5 v dd po wer supp ly i n put. the v dd range for the ad7 997 /ad 799 8 is from 2.7 v to 5.5 v. 6 r e f in voltage referenc e input. t h e exte rnal reference for the ad 799 7/a d 7998 s h ould be a pplied t o this inp u t pin. the vol t age range for the external referenc e is 1.2 v to v dd . a 0.1 f and 1 f ca pacitors s h ould be p l aced betwee n ref in and agnd . see typic a l connec t ion d i agram. 7 v in 1 anal og input 1. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 8 v in 3 anal og input 3. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 9 v in 5 anal og input 5. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 1 0 v in 7 anal og input 7. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 1 1 v in 8 anal og input 8. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 1 2 v in 6 anal og input 6. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 1 3 v in 4 anal og input 4. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 1 4 v in 2 anal og input 2. singl e - e nded analog in put channe l. the input range is 0 v to ref in . 1 5 a s logic inpu t. address select input t h at selects o n e o f three i 2 c addresses for the ad79 97/a d 7 998, as sh own i n tab l e 6 . the device addre ss depends on t h e voltage applied to this pin. 16 convst logic inpu t signal. convert start s i gnal. this is an e d ge-triggered logic input. th e rising edge of this signal po wers up the part. t h e pow e r- up time for the part is 1 s. the falling edge of convst pl ac es the trac k/hol d into hol d m o de and initiates a conversion. a po wer-up time of at l e ast 1 s must be all o wed for the convst high p u lse; otherwise, t h e conversion result is invalid (see the modes of oper ation section). 17 alert/bus y digital output. s e lectab le as an a l ert or bus y out p ut func tion. when c o nfigured as an alert , this pi n ac ts as an out- of- range indic a tor and, if enabl e d, becomes active whe n the conver sion result violat es the da ta hi gh or da tal o w register values. s ee the limit registers section. when co nf igured as a busy outpu t , this pin be comes active whe n a conversion is in progress. open-drain output. 18 sda digital i/o. serial bus bi directiona l data. open-drain output. externa l pull-up resistor required. 19 scl digital inpu t. serial bu s clock. ope n -drain input. ext e rnal pull-u p resistor required. table 6. i 2 c a d d r ess selection part num b er as pin i 2 c addre s s ad7 997 -0 agnd 010 0 001 ad7 997 -0 v dd 010 0 010 ad7 997 -1 agnd 010 0 011 ad7 997 -1 v dd 010 0 100 ad7 997 -x 1 float 010 0 000 ad7 998 -0 agnd 010 0 001 ad7 998 -0 v dd 010 0 010 ad7 998 -1 agnd 010 0 011 ad7 998 -1 v dd 010 0 100 ad7 998 -x 1 f l o a t 0 1 0 0 0 0 0 1 i f the as pin is lef t floa ting on an y of th e ad7997/ad7998 par t s, the devic e addr ess is 010 0000.
ad7997/ad7998 rev. 0 | page 11 of 32 terminology s i g n a l -t o-n o is e an d dis t o r t i o n r a t i o (s in ad) the m e as ur e d r a t i o o f sig n al-t o - n o is e and dist or t i o n a t t h e o u t - p u t o f t h e a/ d co n v er t e r . th e s i g n al is t h e r m s a m pli t ude o f th e fun d a m en tal . n o i s e is th e s u m o f all n o n f un da me n t al si gnal s u p t o half th e s a m p lin g f r e q uen c y (f s /2), excl udin g dc. the ra t i o is dep e n d e n t on t h e n u m b er o f q u a n t i za t i on le vels in t h e dig i t i - za t i on p r o c es s; t h e m o r e l e v e l s, t h e smal ler t h e qua n t i za t i on n o i s e . th e t h eo r e ti cal si gn al- t o-n o i s e a n d d i s t o r ti o n ra ti o f o r a n ide a l n- b i t c o n v er t e r wi t h a sin e wa ve in p u t is g i v e n b y sig n al - to -( no i s e + d i s t or t i on ) = (6.02 n + 1.76) db th us, the s i n a d is 61.96 db f o r a 10-b i t con v er t e r a n d 74 db f o r a 12-b i t con v er t e r . t o t a l ha r m on i c d i s t or t i on ( t h d ) t h e r a t i o of t h e r m s su m of h a r m on i c s to t h e f u n d a me n t a l . f o r th e ad7997 /ad7998, i t is def i n e d as 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 ) db ( + + + + = w h er e v 1 is t h e r m s a m pli t ude o f t h e f u ndam e n t a l and v 2 , v 3 , v 4 , v 5 , a n d v 6 a r e t h e r m s am pli t udes o f t h e s e c o nd t h r o ug h six t h ha r m o n i c s . p e a k h a rmo n i c o r s p uri o us n o is e the ra t i o o f t h e r m s val u e o f t h e n e xt la rg es t com p on e n t i n t h e ad c o u t p u t s p ec tr um (u p t o f s /2 an d excl uding dc) to t h e r m s val u e o f t h e f u ndame n t a l . t y p i c a l l y , t h e v a l u e o f t h i s sp e c if i c a t ion is det e r m i n e d b y t h e la rgest h a r m o n ic in t h e sp e c t r um, b u t fo r ad cs w h er e t h e ha r m o n ic s a r e b u r i e d i n t h e no is e f l o o r , i t is a n o i s e peak. inte r m o d u l at i o n d i s t or t i on w i t h in p u ts co nsis tin g o f sine wa v e s a t tw o f r e q uen c ies, fa a nd fb , an y ac t i ve de vic e w i t h no n l i n e a r i t i es cr e a tes di sto r t i o n p r o d uc ts a t s u m a nd dif f er ence f r e q uen c ies o f mfa nfb , w h er e m, n = 0, 1, 2, 3, a nd s o o n . i n ter m o d u l a t ion disto r t i o n ter m s a r e th ose f o r whic h n e i t h e r m n o r n eq ual zer o . f o r exa m p l e , seco n d -o r d er t e r m s in c l ude (fa + fb) a nd (fa ? fb ) , wh il e thir d-o r der t e r m s in c l ude (2fa + fb), (2fa ? fb),(fa + 2fb) a nd (fa ? 2fb). the ad7997/ad7998 is t e s t e d usin g th e c c if s t anda r d w h er e tw o in p u t f r e q u e n c ies n e a r t h e t o p end o f t h e i n p u t b a n d wi d t h a r e us e d . i n t h i s cas e , t h e s e cond-o r der ter m s ar e usua l l y dis- t a nce d in f r e q u e n c y f r o m t h e o r ig ina l sin e wa ves w h i l e t h e thir d-o r der t e r m s a r e us ual l y a t a f r eq uen c y c l os e t o th e in p u t f r e q uen c ies. a s a r e su l t , t h e s e c o nd an d t h ir d-or der ter m s a r e sp e c if ie d s e p a ra t e ly . t h e c a lc u l a t io n o f in t e r m o d u l a t io n dist o r - ti o n i s , li k e t h e t h d s p eci f ica t io n , th e ra ti o o f th e rm s s u m o f th e in d i v i d u al di s t o r ti o n p r od uct s t o th e rm s a m p l i t ud e o f th e s u m o f t h e f u nda m e n t a ls, exp r es s e d in db . c h an nel-t o -c h a n n el i s ol a t i o n a m e asur e o f t h e le vel o f cr o sst a l k b e tw e e n channels, t a k e n b y a p ply i ng a f u l l - s c a l e s i ne w a v e s i g n a l to t h e u n s e l e c t e d i n put c h a n n e ls, an d det e r m ining h o w m u c h t h e 108 h z sig n al is a t t e n u a t ed i n th e s e l e ct ed c h a n n e l . t h e s i n e w a v e s i gn a l a p p l i e d t o th e uns e lec t e d c h a n ne ls is then va r i ed f r o m 1 kh z u p t o 2 mh z, each tim e det e r m inin g h o w m u ch the 108 h z sig n al in th e s e lec t e d c h anne l is a t ten u a t ed . this f i gur e rep r es en ts t h e w o rs t-c a s e le ve l acr o s s al l c h a n n e ls. ap e r t u r e d e l a y the m e as ur e d i n t e r v al b e twe e n t h e s a m p ling clo c k s le adin g e d g e and t h e p o in t a t w h ich t h e ad c t a k e s t h e s a m p le . a p e r tu r e j i tt e r this is t h e s a m p le-t o-s a m p le v a r i a t ion i n t h e e f fe c t i v e p o in t in t i me a t w h ich t h e s a m p le is t a k e n. fu l l - p o w e r b a n d w i d t h the i n pu t f r e q u e n c y a t w h ich t h e am pl i t u d e o f t h e re c o ns t r uc t e d f u ndam e n t al is r e d u ced b y 0.1 db o r 3 db f o r a f u l l -s cale in p u t. p o w e r su pp l y re j e c t i o n r a t i o ( p sr r ) the ra t i o o f t h e p o w e r in t h e a d c o u t p u t a t t h e f u l l -s cale fr e q u e n c y , f , t o th e p o w e r o f a 200 mv p-p sin e wa v e a p p l ie d to t h e a d c v dd su p p ly of f r e q ue nc y f s : ps rr (db) = 10 log ( pf / pf s ) w h er e pf is th e p o w e r a t f r eq uen c y f in t h e ad c o u t p ut; pf s is th e po w e r a t f r eq ue n c y f s co u p led o n t o the ad c v dd su p p ly . in t e g r a l no n l i n e a r i t y the maxi m u m de v i a t ion f r o m a st ra ig h t li n e p a ssin g t h r o ug h t h e e n d p oin t s of t h e a d c t r a n s f er f u n c t i o n . the end p oin t s a r e z e r o scale , a po in t 1 l s b b e lo w th e f i r s t co d e tra n si ti o n , a n d ful l s c ale , a p o in t 1 ls b a b o v e t h e l a s t co de t r a n si t i o n . d i f f erenti a l n o n l i n e a r i ty the dif f er ence b e tw e e n t h e m e as ur e d and t h e i d e a l 1 ls b c h a n g e be tw een a n y tw o a d j a cen t cod e s i n t h e a d c . off s et e r r o r the devia t ion of th e f i rs t co de t r a n si tio n (00 000) t o (00001) f r o m th e ide a ltha t is, a g nd + 1 l s b . off s et e r r o r ma t c h the dif f er ence i n o f fs et er r o r b e tw e e n an y tw o cha n n e ls. ga in er r o r the devia t ion of th e las t co de tra n si tion (111110) t o (111111) f r o m the ideal (tha t is, ref in ? 1 l s b) a f t e r the o f fs et er r o r has b e e n ad j u s t e d ou t. ga in er r o r m a t c h the dif f er ence i n ga in er r o r b e t w e e n an y tw o cha n n e ls.
ad7997/ad7998 rev. 0 | page 12 of 32 typical perf orm ance cha r acte ristics ?120 ?100 ?8 0 ?6 0 ?4 0 ?2 0 0 s i nad (db) 20 40 06 0 frequency (khz) 03473-0-004 fs = 121ksps fscl = 3.4mhz fin = 10khz snr = 71.84db sinad = 71.68db thd = 86.18db sfdr = ? 88.70db f i g u re 4. a d 79 98 d y nam i c p e r f or ma n c e w i t h 5 v sup p l y and 2 . 5 v re fer e nc e , 121 ksps, mo de 1 ?110 ?9 0 ?7 0 ?5 0 ?3 0 ?1 0 s i nad (db) 10 40 06 0 40 45 50 60 70 75 s i nad (db) 1 1000 frequency (khz) 03473-0-007 100 10 v dd = 4.5v v dd = 3v v dd = 2.7v v dd = 3.3v v dd = 5v 65 55 v dd = 5.5v input frequency (khz) 03473-0-005 20 30 50 fs = 121ksps fscl = 3.4mhz fin = 10khz sinad = 61.63db thd = 91.82db sfdr = ? 94.95db f i g u re 5. a d 79 97 d y nam i c p e r f or ma n c e w i t h 5 v sup p l y and 2 . 5 v re fer e nc e , 121 ksps, mo de 1 20 40 70 80 90 100 p s rr (db) 10 1000 supply ripple frequency (khz) 03473-0-006 100 v dd = 3v v dd = 5v 50 30 60 v dd = 3v/5v 20 0m v p - p s i n e w a v e on v dd 2nf capacitor on v dd f i g u r e 6 . p s r r v s . s u pp l y ripp le f r e q ue n c y f i g u re 7. a d 79 98 si na d v s . a n al og inp u t f r equ e nc y f o r v a ri ous su p p ly v o lt ag es, 3. 4 m h z f scl , 13 6 k s ps ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 inl e rror (ls b ) 20 00 1 500 5 0 0 1 000 0 2 5 0 0 300 0 350 0 4000 code 03473-0-008 fi g u r e 8 . t y p i c a l i n l , v dd = 5.5 v , m o d e 1, 3. 4 m h z f scl , 121 ksps ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 dnl e rror (ls b ) 2000 150 0 500 100 0 0 2500 3000 3500 4000 code 03473-0-009 fi g u r e 9 . t y p i c a l d n l , v dd = 5. 5 v , m o de 1, 3. 4 m h z f scl , 1 21 k s ps
ad7997/ad7998 rev. 0 | page 13 of 32 ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 inl e rror (ls b ) 2 000 15 00 500 100 0 0 2500 300 0 3 5 0 0 4 000 code 03473-0-010 f i g u re 10. t y pic a l i n l, v dd = 2. 7 v , m o de 1, 3. 4 m h z f scl , 1 21 k s ps ? 1.0 ? 0.8 ? 0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 dnl e rror (ls b ) 2 000 15 00 5 0 0 100 0 0 2500 300 0 3 5 0 0 4000 code 03473-0-011 f i g u re 11. t y pic a l d n l, v dd = 2. 7 v , m o de 1, 3. 4 m h z f scl , 1 21 k s ps inl e rror (ls b ) reference voltage (v) 03473-0-012 ? 1.0 ? 0.8 -0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 positive inl negative inl f i gur e 1 2 . ad79 98 cha n ge i n inl vs . re fe r e nc e v o l t a g e v dd = 5 v , m o de 1, 12 1 k s ps dnl e rror (ls b ) reference voltage (v) 03473-0-013 ? 1.0 ? 0.8 -0.6 ? 0.4 ? 0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.7 2.2 2.7 3.2 3.7 4.2 4.7 positive dnl negative dnl f i gur e 1 3 . ad79 98 cha n ge i n dnl vs . re fe r e nc e v o l t a g e v dd = 5 v , m o de 1, 12 1 k s ps s u p p l y curre nt (ma) supply voltage (v) 03473-0-014 0 0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 2.7 3.2 3.7 4.2 4.7 5.2 +25 c +85 c ?4 0 c f i gur e 1 4 . ad79 98 sh ut do wn curr e n t vs . suppl y v o l t a g e , C 4 0c, +25c, and +85c s u p p l y curre nt (ma) scl frequency (khz) 03473-0-015 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 100 600 1100 1600 2100 2600 3100 mode 1 vdd = 5v mode 1 vdd = 3v mode 2 vdd = 5v mode 2 vdd = 3v f i gur e 1 5 . ad79 98 a v e r a g e suppl y c u r r ent vs . i 2 c bus r a te for v dd = 3 v a n d 5 v
ad7997/ad7998 rev. 0 | page 14 of 32 s u p p l y curre nt (ma) supply voltage (v) 03473-0-016 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.7 3.2 3.7 4.2 4.7 5.2 mode 2 - 147ksps mode 1 - 121ksps temperature = +85 c temperature = +25 c temperature = ? 40 c temperature = +85 c temperature = +25 c temperature = ? 40 c f i gure 16. a d 7 9 9 8 a v er age sup p l y cu rr e n t v s . sup p ly v o l t age for v a ri ous t e mper atur es 03473-0-017 10.4 10.6 10.8 11.0 11.2 11.4 11.6 11.8 12.0 1.200 2.048 2.500 2.700 3.000 3.300 4.096 4.500 5.000 reference voltage (v) enob ( b its) 68 69 70 71 72 73 74 s i nad (db) enob v dd = 3v enob v dd = 5v sinad v dd = 3v sinad v dd = 5v f i g u re 17. sina d/e n ob v s . r e f e r e nc e v o lt ag e , m o de 1, 1 21 k s ps
ad7997/ad7998 rev. 0 | page 15 of 32 circuit i n forma t ion the ad7997/ad7998 a r e lo w p o w e r , 10- a n d 12-b i t, sin g le- s u p p l y , 8-cha n ne l a / d con v er t e rs. th e p a r t s can b e o p er a t e d f r o m a 2.7 v t o 5.5 v s u p p l y . the ad7997/ad7998 ha v e a n 8-c h a n n e l m u l t i p lexer , a n o n - chi p t r ack - an d - h o ld , an a / d con v er t e r , a n on-chi p os ci l l a t o r , in ter n a l d a t a r e g i sters, a nd an i 2 c - c o m p a t i b l e se ri al i n t e rf a c e , all h o us e d in a 20-l e ad t ssop . t h is p a cka g e o f fers co n s idera b le s p ace-s a vin g adva n t a g es o v er al t e r n a t i v e s o l u t i on s. th e ad7997/ad79 98 r e q u ir e a n ex t e r n al r e f e r e n c e in t h e ra n g e o f 1.2 v t o v dd . the ad7997/ad7998 typ i c a l l y r e ma in in a p o w e r - do wn s t a t e w h i l e not c o n v e r t i ng . whe n suppl i e s are f i r s t a ppl i e d, t h e p a r t s co m e u p in a p o w e r - do w n st a t e . p o w e r - u p is ini t ia t e d p r io r t o a con v ersio n , and t h e de vi ce r e t u r n s t o s h u t dow n w h e n t h e co n v ersio n is com p let e . c o n v ersio n s can be ini t ia t e d o n t h e ad7997/ad79 98 b y p u lsin g the co n v s t sig n al , usin g a n a u t o ma t i c c y cle in t e r v al m o de , o r a co mmand m o de w h er e wa k e -u p and a co n v ersio n o c c u r d u r i n g a wr i t e addr ess f u n c t i on (s e e t h e m o des o f o p e r a t io n s e c t io n). w h en t h e co n v ersio n is com p let e , t h e ad7997/ad7998 aga i n en t e r sh u t do w n m o de. this a u to ma t i c sh u t do wn fe a t u r e a l lo ws p o w e r s a v i n g be tw e e n co n v ersio n s. this m e an s an y r e ad o r wr i t e o p era t ion acr o s s t h e i 2 c in t e r f ace can o c c u r w h i l e t h e de vic e is in sh u t down. c o nverter oper a t ion the ad7997/ad7998 a r e s u cc es si v e a p p r o x ima t io n a n alog-t o- dig i t a l con v er te rs b a s e d a r o u nd a ca p a c i t i ve d a c. f i gur e 18 a nd f i gur e 19 sh o w sim p l i f i e d s c h e ma tic s o f th e ad c d u r i n g t h e ac q u isi t ion a nd con v ersio n phas e, r e sp e c t i vely . f i gur e 18 sh o w s t h e ac q u isi t io n pha s e . s w 2 is clos e d and sw1 is in p o si tio n a, th e co m p a r a t o r is he ld in a ba lan c e d con d i t io n, a nd t h e s a m p ling ca p a c i t o r acquir es t h e sig n al o n v in . capacitive dac v in comparator control logic sw1 a b sw2 ag nd 03473-0-018 f i g u re 18. a d c ac quis it i o n p h as e a t th e b e g i nning o f a co n v ersion, sw2 o p en s and sw1 m o v e s t o p o si tio n b , c a usin g th e com p a r a t o r t o become un b a lan c e d , as sh own i n f i gur e 19. th e in p u t is dis c o n n e c t e d on ce t h e co n- v e rsio n b e g i n s . the co n t r o l log i c a nd t h e c a p a ci t i v e d a c a r e us e d t o ad d an d sub t rac t f i xe d am o u n t s o f cha r ge f r o m t h e s a m p ling c a p a ci t o r t o b r in g t h e co m p a r a t o r back in t o a b a l a nc e d c o nd i t i o n . whe n t h e c o m p ar a t or i s re b a l a nc e d , t h e co n v ersio n is com p let e . the co n t r o l log i c g e n e ra t e s th e ad c o u t p u t co de . f i g u r e 20 s h o w s t h e ad c tra n sf er c h a r ac t e r i s t ic. v in comparator control logic sw1 a b sw2 a gn d capacitive dac 03473-0-019 f i g u re 19. a d c co nvers i on p h as e adc transfer function the o u t p u t co din g o f th e ad79 97/ad7998 is s t ra ig h t b i na r y . the desig n e d c o de tra n si t i o n s o c c u r a t s u cces s i v e in t e g e r l s b val u es (1 ls b , 2 ls b , an d s o on). the ls b size is ref in /1024 f o r th e ad7997 and ref in /4096 f o r th e ad7998. f i gur e 20 s h o w s th e ideal tra n sf er c h a r ac t e r i s t ic f o r th e ad7997/ad7998. 000 ... 000 adc code an alog input 0v to ref in 111...111 000 ... 001 000 ... 010 111 ... 110 111 ... 000 011...111 agnd + 1lsb +ref in ? 1lsb ad7998 1lsb = ref in /4096 03473-0-020 ad7997 1lsb = ref in /1024 f i gur e 2 0 . ad79 97 /ad7 99 8 t r a n sfe r cha r a c te r i stic
ad7997/ad7998 rev. 0 | page 16 of 32 t y p i c a l c o nnec t i o n di a g r a m the typ i cal co nn ec tion dia g ra m f o r th e ad79 97/ad7998 is sh own i n f i gur e 22. i n t h is f i gur e , t h e a ddr ess s e le c t p i n ( a s) is t i e d t o v dd ; ho w e v e r , a s can als o be tie d t o a g nd o r lef t f l o a tin g , al lo wing th e us er t o s e l e c t u p t o f i v e ad7997/ad7998 de vices on t h e s a me s e r i al b u s. an ext e r n al r e fer e n c e m u s t b e a p p l ie d t o t h e ad7997/ad7998. this r e f e r e n c e ca n be in t h e ra n g e o f 1.2 v to v dd . a p r e c isio n r e fer e n c e li k e t h e ref 19x fa mil y , ad780, ad r03, o r adr381 can b e us e d t o s u p p l y t h e re f e re nc e vo lt ag e to t h e a d c . s d a and scl fo r m t h e 2- w i r e i 2 c-/s mb us- c om p a t i b l e i n te r f a c e. e x te r n a l pu l l - u p re s i ste r s are re qu i r e d for b o t h sd a a nd scl li n e s. the ad7998-0/ad7997-0 su p p o r t s t a nda rd and fas t i 2 c in t e r f ace m o des . th e ad7998 -1 /ad7997 -1 s u p p o r t s t anda r d , f a st, and hig h sp e e d i 2 c i n ter f ace m o des. th er efo r e if o p era t in g in ei t h er standar d o r fas t m o de , u p t o f i v e ad7 997/ad7998 de vices c a n b e c o nn e c te d to t h e b u s, as n o te d: 3 ad7997-0 / ad7998-0 and 2 ad7997-1 / ad7998-1 or 3 ad7997-1 / ad7998-1 and 2 ad7997-0 / ad7998-0 i n hig h sp ee d mo de , u p t o thr e e ad7997-1 / ad7 998-1 de vices ca n b e con n e c te d to t h e b u s. w a k e - u p f r o m sh u t down and ac q u isi t io n p r io r to a co n v ersion is a p p r o x im a t e l y 1 s, a n d con v ersio n t i m e is a p p r o x ima t e l y 2 s. th e ad79 97/ad7998 en ters s h u t down mo de a g ain a f t e r e a ch con v ersio n , w h ich is us ef u l in a p plic a t io n s w h er e p o w e r co n s um p t io n is a con c er n. anal og input f i gur e 21 s h o w s a n eq u i valen t cir c ui t o f th e ad7997/ad7998 a n a l o g in p u t st r u c t ur e. the tw o dio d es, d1 and d2, p r o v ide es d p r o t ecti o n f o r th e a n alog i n p u t s . c a r e m u st be ta k e n t o en s u r e t h a t t h e a n alog in p u t sig n al do es n o t exce e d t h e su p p l y ra ils b y m o r e tha n 300 mv . this ca us es t h e dio d es t o become fo r w a r d b i a s e d a nd st a r t co nd u c t i n g c u r r en t in to t h e subst r a t e. th e s e di o d es c a n con d uc t a maxim u m c u r r en t o f 10 ma wi t h o u t c a usin g ir r e v e rsi b le dama ge t o t h e p a r t . v in d1 v dd d2 r1 c2 30pf c1 4pf conversion phase?switch open track phase?switch closed 03473-0-022 f i g u re 21. equiv a le nt a n al og input c i rcuit c a p a ci t o r c1 in f i gur e 21 is typ i cal l y a b o u t 4 p f a n d can pr i m ar i l y b e att r ibute d to pi n c a p a c i t a nc e. r e s i s t or r 1 i s a l u m p e d com p on en t made u p of th e o n r e sis t ance (r on ) o f a t r ack- an d - h o l d s w i t ch, and a l s o in cl udes t h e r on of t h e in p u t m u l t i p lexer . th e t o tal r e sis t an ce is typ i cal l y a b o u t 400 ?. c 2 , th e a d c s a m p l i n g c a pa ci t o r , h a s a t y p i cal ca pa c i ta n c e o f 30 pf . v dd v in 1 agnd 5v supply ref 19x 1 f 0.1 f 10 f ad7997/ ad7998 0v to ref in input sda c/ p scl 2-wire serial interface convst alert ref in r p r p r p v dd as v in 8 03473-0-021 0.1 f f i gur e 2 2 . ad79 97 /ad7 99 8 t y pi c a l c o nne ctio n d i a g r a m
ad7997/ad7998 rev. 0 | page 17 of 32 f o r a c a p pl i c a t i o ns , re mov i ng h i g h f r e q u e nc y c o m p o n e n t s f r om t h e a n a l og in p u t sig n a l is r e co mmende d , b y usin g a n rc b a nd- p a ss f i l t er on t h e r e l e van t a n alog i n pu t pi n. i n a p plic a t i o ns w h er e h a r m on i c d i stor t i on a n d s i g n a l - t o - noi s e r a t i o ar e c r it i c a l , t h e an a l o g i n put s h ou l d b e d r ive n f r om a l o w i m p e d a nc e s o u r c e . l a rg e s o ur ce i m p e dan c es sig n if i c a n t l y a f fe c t t h e ac p e r f o r ma n c e o f t h e a d c. thi s ma y ne ces s i t a t e t h e us e o f an i n p u t b u f f er a m pl i f i e r . t h e c h oi c e of t h e op a m p i s a f u n c t i o n of t h e p a r t i c u l a r ap p l i c at i o n . w h en n o am pli f ier is us e d t o dr i v e t h e a n alog in p u t, t h e s o ur ce i m p e dan c e sho u ld b e li mi te d t o l o w v a l u es. the max i m u m s o urc e i m p e d a nc e d e p e nd s o n t h e a m ou n t of tot a l h a r m on i c d i s t or t i on (thd) t h a t c a n b e t o ler a te d . thd in cr eases as t h e so ur ce im p e d - a n c e i n cr e a s e s, a nd p e r f o r ma n c e deg r ades. f i gu r e 23 s h o w s t h e th d vs . t h e a n al og in p u t si g n al f r eq uen c y w h en us in g s u p p l y v o l t ag es o f 3 v 10 % and 5 v 10 %. fi g u re 2 4 s h ow s t h e t h d vs. t h e a n alog i n p u t sig n al f r e q uen c y fo r dif f er en t s o ur ce im p e d a n c es. ?100 ?9 0 ?8 0 ?7 0 ?5 0 ?4 0 thd (db) 10 1000 input frequency (khz) 03473-0-023 100 ?6 0 v dd = 5.5v v dd = 5v v dd = 4.5v v dd = 3.3v v dd = 3v v dd = 2.7v f i g u re 23. th d v s . a n al og input f r equ e nc y f o r v a ri ous sup p ly v o lt ag es, f s = 136 ksp s , mo de 1 ?100 ?9 0 ?8 0 ?7 0 ?5 0 ?4 0 thd (db) 10 1000 input frequency (khz) 03473-0-024 100 ?6 0 r in = 50 ? r in = 10 ? r in = 100 ? r in = 1000 ? v dd = 5v f i g u re 24. th d v s . a n al og input f r equ e nc y f o r v a ri ous s o u r c e impedanc es for v dd = 5 v , 13 6 ksp s , m o de 1
ad7997/ad7998 rev. 0 | page 18 of 32 internal register structure the ad7997/ad7998 co n t ain 17 in t e r n al r e g i st ers tha t a r e us e d t o s t o r e con v ersio n r e s u l t s, hig h a nd lo w co n v ersio n limi ts, an d info r m a t io n to co nf igur e a nd c o n t r o l t h e d e vic e (s e e f i gur e 25 ). sixt e e n a r e da t a r e g i st ers an d on e is an ad dr ess p o in t e r r e g i st er . e a ch da t a reg i ster has an address t h a t t h e addr ess p o in t e r reg i s t e r p o in ts t o w h e n co mm uni c a t in g wi t h i t . t h e con v ersio n r e su l t r e g i s t er is the o n l y da ta r e g i st er tha t is r e ad only . address pointer register b e ca us e i t is t h e r e g i s t er t o w h ich t h e f i rs t da t a b y t e o f e v er y wr i t e op era t io n is wr i t t e n a u t o ma t i c a l l y , t h e addr es s p o i n t e r r e g i ster do es n o t ha ve and do es n o t r e q u ir e a n a ddr ess. t h e addr es s p o in ter r e g i s t er is a n 8 - b i t r e g i s t er i n w h ich t h e 4 ls b s are u s e d a s p o i n te r b i t s to store an a d dre s s t h a t p o i n t s to one of th e ad7997 /ad7998 s da ta r e g i s t ers. the 4 m s bs a r e us ed as co mman d b i ts w h en op era t i n g in m o de 2 (s e e t h e m o de s o f o p era t ion s e c t i o n). the f i rs t b y t e fol l o w in g e a ch wr i t e addr es s is t o t h e addr es s p o in t e r r e g i s t er , co n t a i nin g t h e addr es s o f o n e o f t h e da t a r e g i st ers. the 4 ls bs s e le c t t h e da t a reg i s t er t o w h ich s u b s eq u e n t d a ta b y t e s a r e w r i t t e n . o n l y th e 4 l s b s o f th i s r e gi s t e r a r e us ed t o s e le c t a da t a r e g i s t er . on p o w e r - u p , th e addr es s p o in t e r r e g i s t er co n t a i n s al l 0s, p o in t i n g t o t h e co n v ersio n r e s u l t re g i ste r . tab l e 7. add r ess poin ter register c 4 c 3 c 2 c 1 p 3 p 2 p 1 p 0 0 0 0 0 register s e l e c t table 8. ad79 97/ad7998 re gister addresses p 3 p 2 p 1 p 0 r e g i s t e r s 0 0 0 0 conversi on result register (rea d) 0 0 0 1 alert status reg i ster (read/write) 0 0 1 0 configuration register (read/write) 0 0 1 1 cycle timer register (read/write) 0 1 0 0 data low reg c h 1 (read/ write) 0 1 0 1 data high reg c h 1 (read/ write) 0 1 1 0 hysteresis reg ch1 (read/write) 0 1 1 1 data low reg c h 2 (read/ write) 1 0 0 0 data high reg c h 2 (read/ write) 1 0 0 1 hysteresis reg ch2 (read/write) 1 0 1 0 data low reg c h 3 (read/ write) 1 0 1 1 data high reg c h 3 (read/ write) 1 1 0 0 hysteresis reg ch3 (read/write) 1 1 0 1 data low reg c h 4 (read/ write) 1 1 1 0 data high reg c h 4 (read/ write) 1 1 1 1 h y s t e r e s i s reg ch4 ( r e a d / w r i t e ) co nf ig ur at io n re gi st er address pointer register serial bu s i nterface sda scl d a t a data low regi ster ch2 da ta high regi ster ch2 data low re gister ch 1 hy steresis regi ster ch1 data high regi ster ch1 cycle t i m er regist er al ert s tatus register conversion result register hy steresis regi ster ch2 da ta high regi ster ch3 da ta low regist er ch 3 hy steresis regi ster ch3 data high regist er ch4 data low regi ster ch4 hysteresis regist er ch 4 03473-0-025 f i gur e 2 5 . ad79 97 /ad7 99 8 re gi st er st r u ctur e
ad7997/ad7998 rev. 0 | page 19 of 32 configuration register the configuration register is a 16-bit read/write register that is used to set the operating mode of the ad7997/ad7998. the 4 m sbs of the register are unused. the bit functions of all 12 lsbs of the configuration register are outlined in table 9. a 2-byte write is necessary when writing to the configuration register. table 9. configuration register bits and default settings at power-up d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 dontc dontc dontc dontc ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 fltr alert en busy/ alert alert/busy polarity 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 table 10. bit function descriptions bit mnemonic comment d11 to d4 ch8 to ch1 these 8-channel address bits select the analog input channe l(s) to be converted. a 1 in any of bits d11 to d4 selects a channel for conversion. if more than on e channel bit is set to 1, the ad7997/ad7998 sequence through the selected channels, starting with the lowest channel. all unused channels should be set to 0. prior to initiating a conversion, a channel or channels for con version must be selected in the configuration register. d3 fltr the value written to this bit of the control register determines whether the filtering on sda and scl is enabled or is to be bypassed. if this bi t is a 1, then the filtering is enabled; if it is a 0, the filtering is bypassed. d2 alert en the hardware alert function is en abled if this bit is set to 1, and disabled if this bit is set to 0. this bit is used in conjunction with the busy/alert bit to determine if the alert/busy pin acts as an alert or a busy output (see table 12). d1 busy/alert this bit is used in conjunction with the alert en bit to determine if the alert/ busy output, pin 17, acts as an alert or busy output (see table 12), an d if pin 17 is configured as an alert output pin, if it is to be reset. d0 busy/alert polarity this bit determines the active polari ty of the alert/busy pin regardless of whether it is configured as an alert or busy output. it is active low if this bi t is set to 0, and active high if set to 1. table 11. channel selection d11 d10 d9 d8 d7 d6 d5 d4 selected analog input channel comments 0 0 0 0 0 0 0 1 convert on channel 1 (v in 1) 0 0 0 0 0 0 1 0 convert on channel 2 (v in 2) 0 0 0 0 0 1 0 0 convert on channel 3 (v in 3) 0 0 0 0 1 0 0 0 convert on channel 4 (v in 4) 0 0 0 1 0 0 0 0 convert on channel 5 (v in 5) 0 0 1 0 0 0 0 0 convert on channel 6 (v in 6) 0 1 0 0 0 0 0 0 convert on channel 7 (v in 7) 1 0 0 0 0 0 0 0 convert on channel 8 (v in 8) if more than one channel is selected, the ad7997/ad7998 start converting on the selected sequence of channels starting with the lowest channel in the sequence. table 12. alert/busy function d2 d1 alert/busy pin configuration 0 0 pin does not provide any interrupt signal. 0 1 pin configured as a busy output. 1 0 pin configured as an alert output. 1 1 resets the alert output pin, the alert_flag bit in the conversion result register , and the entire alert status register (if any is active). if 1/1 is written to bits d2/d1 in the configuration register to reset the alert pin, the alert_flag bit, and the alert status register, the contents of the configuration register read 1/0 for d2/d1, respectively, if read back.
ad7997/ad7998 rev. 0 | page 20 of 32 conversion result register the conversion result register is a 16-bit, read-only register that stores the conversion result from the adc in straight binary format. a 2-byte read is necessary to read data from this register. table 13 shows the contents of the first byte to be read from the ad7997/ad7998, and table 14 shows the contents of the second byte to be read. table 13. conversion value register (first read) d15 d14 d13 d12 d11 d10 d9 d8 alert_flag ch id2 ch id1 ch id0 m s b b10 b9 b8 table 14. conversion value register (second read) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 the ad7997/ad7998 conversion resu lt consists of an alert_flag bit, three channel identifier bits, and the 10- and 12-bit data result (msb first). for the ad7997, the 2 lsbs (d1 and d0) of the second read contain two 0s. the three channel identification bits can be used to identify to which of the eight analog input channels the conversion result corresponds. the alert_flag bit indicates whether the conversion result being read or any other channel result has violated the limit registers associated with it. if an alert occurs, the master can read the alert status register to obtain more information on where the alert occurred. limit registers the ad7997/ad7998 have four pairs of limit registers. each pair stores high and low conversion limits for the first four analog input channels, ch1 to ch4. each pair of limit registers has one associated hysteresis register. all 12 registers are 16 bits wide; only the 12 lsbs of the registers are used for the ad7997 and ad7998. for the ad7997, the 2 lsbs, d1 and d0 in these registers, should contain 0s. on power-up, the contents of the data high register for each channel is full scale, while the contents of the data low registers is zero scale by default. the ad7997/ad7998 signal an alert (in either hardware, software, or both depending on configuration) if the conversion result moves outside the upper or lower limit set by the limit registers. there are no limit registers or hysteresis registers associated with ch5 to ch8. data high register ch1/ch2/ch3/ch4 the data high registers for ch1 to ch 4 are 16-bit read/write registers; only the 12 lsbs of each register are used. this register stores the upper limit that activates the alert output and/or the alert_flag bit in the conversion result register. if the value in the conversion result register is greater than the value in the data high register, an alert occurs for that channel. when the conversion result returns to a value at least n lsbs below the data high register value, the alert output pin and alert_flag bit are reset. the value of n is taken from the hysteresis register associated with that channel. the alert pin can also be reset by writing to bits d2 and d1 in the configuration register. for the ad7997, d1 and d0 of the data high register should contain 0s. table 15. data high register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 16. data high register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 data low register ch1/ch2/ch3/ch4 the data low register for each channel is a 16-bit read/write register; only the 12 lsbs of each register are used. the register stores the lower limit that activates the alert output and/or the alert_flag bit in the conversion result register. if the value in the conversion result register is less than the value in the data low register, an alert occurs for that channel. when the conversion result returns to a value at least n lsbs above the data low register value, the alert output pin and alert_flag bit are reset. the value of n is taken from the hysteresis register associated with that channel. the alert output pin can also be reset by writing to bits d2 and d1 in the configuration register. for the ad7997, d1 to d0 of the data low register should contain 0s. table 17. data low register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 18. data low register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0
ad7997/ad7998 rev. 0 | page 21 of 32 hysteresis register (ch1/ch2/ch3/ch4) each hysteresis register is a 16-bit read/write register, of which only the 12 lsbs are used. the hysteresis register stores the hysteresis value, n, when using the limit registers. each pair of limit registers has a dedicated hysteresis register. the hysteresis value determines the reset point for the alert pin/alert_flag if a violation of the limits has occurred. for example, if a hysteresis value of 8 lsbs is required on the upper and lower limits of channel 1, the 12-bit word, 0000 0000 0000 1000, should be written to the hysteresis register of ch1, the address of which is shown in table 8. on power-up, the hysteresis registers contain a value of 2 for the ad7997 and a value of 8 for the ad7998. if a different hysteresis value is required, that value must be written to the hysteresis register for the channel in question. for the ad7997, d1 and d0 of the hysteresis register should contain 0s. table 19. hysteresis register (first read/write) d15 d14 d13 d12 d11 d10 d9 d8 0 0 0 0 b11 b10 b9 b8 table 20. hysteresis register (second read/write) d7 d6 d5 d4 d3 d2 d1 d0 b7 b6 b5 b4 b3 b2 b1 b0 using the limit registers to store min/max conversion results for ch1 to ch4 if full scale, that is, all 1s, is written to the hysteresis register for a particular channel, the data high and data low registers for that channel no longer act as limit registers as previously described, but instead act as storage registers for the maximum and minimum conversion results returned from conversions on a channel over any given period of time. this function is useful in applications where the widest span of actual conversion results is required rather than using the alert to signal that an intervention is necessary. this function could be useful for monitoring temperature extremes during refrigerated goods transportation. it must be noted that on power-up, the contents of the data high register for each channel are full scale, while the contents of the data low registers are zero scale by default. therefore, minimum and maximum conversion values being stored in this way are lost if power is removed or cycled. alert status register (ch1 to ch4) the alert status register is an 8-bit, read/write register that provides information on an alert event. if a conversion result activates the alert pin or the alert_flag bit in the conversion result register, as described in the limit registers section, the alert status register may be read to gain further information. the alert status register contains two status bits per channel, one corresponding to the data high limit and the other to the data low limit. the bit with a status of 1 shows where the violation occurredthat is, on which channeland whether the violation occurred on the upper or lower limit. if a second alert event occurs on the other channel between receiving the first alert and interrogating the alert status register, the corresponding bit for that alert event is also set. the alert status register only contains information for ch1 to ch4 because these are the only channels with associated limit registers. the entire contents of the alert status register can be cleared by writing 1,1, to bits d2 and d1 in the configuration register, as shown in table 12. this may also be done by writing all 1s to the alert status register itself. thus, if the alert status register is addressed for a write operation, which is all 1s, the contents of the alert status register are cleared or reset to all 0s. table 21. alert status register d7 d6 d5 d4 d3 d2 d1 d0 ch4 hi ch4 lo ch3 hi ch3 lo ch2 hi ch2 lo ch1 hi ch1 lo table 22. alert status regist er bit function description bit mnemonic if bit is set to 1 violation of d0 ch1 lo data low limit on channel 1. no violation if bit is set to 0. d1 ch1 hi data high limit on channel 1. no violation if bit is set to 0. d2 ch2 lo data low limit on channel 2. no violation if bit is set to 0. d3 ch2 hi data high limit on channel 2. no violation if bit is set to 0. d4 ch3 lo data low limit on channel 3. no violation if bit is set to 0. d5 ch3 hi data high limit on channel 3. no violation if bit is set to 0. d6 ch4 lo data low limit on channel 4. no violation if bit is set to 0. d7 ch4 hi data high limit on channel 4. no violation if bit is set to 0.
ad7997/ad7998 rev. 0 | page 22 of 32 cycle timer register the cycle timer register is an 8-bit, read/write register that stores the conversion interval value for the automatic cycle interval mode of the ad7997/ad7998 (see the modes of operation section). d5 to d3 of the cycle timer register are unused and should contain 0s at all times. on power-up, the cycle timer register contains all 0s, thus disabling automatic cycle operation of the ad7997/ad7998. to enable automatic cycle mode, the user must write to the cycle timer register, selecting the required conversion interval by programming bits d2 to d0. table 23 shows the structure of the cycle timer register, while table 24 shows how the bits in this register are decoded to provide various automatic sampling intervals. table 23. cycle timer register and defaults at power-up d7 d6 d5 d4 d3 d2 d1 d0 sample delay bit trial delay 0 0 0 cyc bit2 cyc bit1 cyc bit0 0 0 0 0 0 0 0 0 table 24. cycle timer intervals d2 d1 d0 typical conversion interval (t convert = conversion time) 0 0 0 mode not selected 0 0 1 t convert 32 0 1 0 t convert 64 0 1 1 t convert 128 1 0 0 t convert 256 1 0 1 t convert 512 1 1 0 t convert 1024 1 1 1 t convert 2048 sample delay and bit trial delay it is recommended that no i 2 c bus activity occurs when a conversion is taking place. however, if this is not possible, for example when operating in mode 2 or mode 3, then in order to maintain the performance of the adc, bits d7 and d6 in the cycle timer register are used to delay critical sample intervals and bit trials from occurring while there is activity on the i 2 c bus. this results in a quiet period for each bit decision. in certain cases where there is excessive activity on the interface lines, this may have the effect of increasing the overall conversion time. however, if bit trial delays extend longer than 1 s, the conversion terminates. when bits d7 and d6 are both 0, the bit trial and sample interval delaying mechanism is implemented. the default setting of d7 and d6 is 0. to turn off both delay mechanisms, set d7 and d6 to 1. table 25. cycle timer register and defaults at power-up d7 d6 d5 d4 d3 d2 d1 d0 sample delay bit trial delay 0 0 0 cyc bit 2 cyc bit 1 cyc bit 0 0 0 0 0 0 0 0 0
ad7997/ad7998 rev. 0 | page 23 of 32 serial interface control of the ad7997/ad7998 is carried out via the i 2 c- compatible serial bus. the devices are connected to this bus as slave devices under the control of a master device, such as the processor. serial bus address like all i 2 c-compatible devices, the ad7997/ad7998 have a 7-bit serial address. the 3 msbs of this address for the ad7997/ ad7998 are set to 010. the ad7997/ad7998 come in two versions, the ad7997-0/ad7997-0 and ad7997-1ad7998-1. the two versions have three different i 2 c addresses available, which are selected by either tying the address select pin, as, to agnd or v dd , or by letting the pin float (see table 6). by giving different addresses for the two versions, up to five ad7997/ ad7998 devices can be connected to a single serial bus, or the addresses can be set to avoid conflicts with other devices on the bus. (see table 6.) the serial bus protocol operates as follows. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line sda, while the serial clock line, scl, remains high. this indicates that an address/data stream follows. all slave peripherals connected to the serial bus responds to the start condition and shift in the next eight bits, consisting of a 7-bit address (msb first) plus an r/ w bit that determines the direction of the data transfer, that is, whether data is written to or read from the slave device. the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit. all other devices on the bus remain idle while the selected device waits for data to be read from or written to it. if the r/ w bit is a 0, the master writes to the slave device. if the r/ w bit is a 1, the master reads from the slave device. data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the receiver of data. transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to-high transition when the clock is high may be interpreted as a stop signal. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device pulls the data line high during the low period before the ninth clock pulse. this is known as no acknowledge. the master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition. any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation, because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
ad7997/ad7998 rev. 0 | page 24 of 32 writing to the ad7997/ad7998 de pen d i n g o n th e r e gi st e r b e i n g w r i t t e n t o , th er e a r e th r e e dif f er en t wr i t es f o r th e ad7997 /ad7998. writing t o the addre ss pointer register for a subsequent read i n o r der t o r e ad f r o m a p a r t ic u l a r r e g i s t er , t h e addr es s p o i n t e r r e g i ster m u st f i r s t co n t a i n t h e a ddr ess o f t h a t r e g i ster . i f i t do es n o t, t h e co r r e c t addr ess m u st b e wr i tte n to t h e a ddr ess p o i n ter r e g i s t er b y p e r f o r min g a sin g le -b yt e wr i t e op era t io n, as sh o w n in f i gur e 26. the wr i t e o p er a t ion co n s is ts o f t h e s e r i al b u s addr ess fol l o w e d b y t h e a ddr ess p o in ter b y te. n o da t a is wr i tte n t o an y o f t h e da t a reg i st ers. a re ad o p er a t ion ma y b e sub s e q u e n t l y p e r f or me d to re a d t h e re g i st e r of i n te re st . writing a s i ngle b y te of d a t a t o the alert st a t us register or c y cle register the a l er t st a t us r e g i st er and c y cl e reg i s t er a r e b o t h 8 - b i t reg i st ers, s o on ly one by t e of d a t a c a n b e w r itte n to e a ch . w r it i n g a s i ng l e by te of d a t a to one of t h e s e re g i s t e r s c o ns i s t s of t h e s e r i a l bu s wr i t e addr es s, t h e ch os e n da t a r e g i s t er addr es s wr i t t e n t o t h e addr es s p o in ter r e g i s t er , fol l o w e d b y t h e da t a b y t e wr i t ten t o t h e s e le c t e d da t a r e g i s t er . s e e f i gure 27. writing t w o b y tes o f d a t a t o a limit , h y steresis, or c o nfig ur a t ion re gister e a c h o f th e fo ur limi t r e g i st ers ar e 16-b i t r e g i s t e r s, s o tw o b y t e s o f da t a a r e r e q u ir e d t o wr i t e a v a l u e t o a n y on e o f t h em. w r i t ing tw o b y t e s o f da t a t o o n e o f t h es e r e g i s t ers co n s i s ts o f t h e s e r i al b u s wr i t e addr es s, t h e ch os e n li mi t r e g i st er addr es s wr i t t e n t o t h e a ddre s s p o i n te r re g i ste r , fol l owe d b y t w o d a t a b y te s w r i tte n t o t h e s e le c t e d da t a r e g i s t er . s e e f i gur e 28. i f th e mas t er is wr i t e addr es sing th e ad7997 /ad7998, i t ca n wr i t e t o m o r e t h a n on e r e g i st er wi t h o u t r e addres sin g t h e a d c. af t e r t h e f i rs t w r i t e o p era t io n has co m p lete d for t h e f i rs t da t a r e g i s t er , d u r i n g t h e n e xt b y t e t h e mas t er sim p l y wr i t es t o t h e addr es s p o in ter b y t e t o s e le c t t h e n e xt da t a r e g i st er fo r a wr i t e o p era t ion. this e l imina t es t h e ne e d t o r e addr es s t h e de vice in ord e r to w r ite t o anot he r d a t a re g i ste r . s da start by master ack. by ad7997/ad7998 ack. by ad7997/ad7998 stop by master frame 1 serial bus address byte frame 2 address pointer register byte 19 1 9 c4 c3 c2 p2 p1 p0 a0 a1 a2 a3 0 0 scl 1 c1 p3 03473-0-026 r/w f i g u re 26. w r it ing t o t h e addres s p o int e r r e g i s t er to s e le c t a r e g i s t er f o r a su bs equent r e ad o p er at ion sda ac k. by ad7997/ad7998 11 9 9 c4 c3 c2 p2 p1 p0 r/w a0 a1 a2 a3 0 0 scl 1 c1 p3 91 9 d7 d6 d5 d2 d1 d0 d4 d3 frame 3 data byte scl (continued) sda (continued) 03473-0-027 start by master ack. by ad7997/ad7998 ack. by ad7997/ad7998 stop by master frame 1 serial bus address byte frame 2 address pointer register byte f i gure 27. sing l e -b yte write s e quen c e
ad7997/ad7998 rev. 0 | page 25 of 32 sda ack. by ad7997/ad7998 ack. by ad7997/ad7998 11 9 9 c4 c3 c2 p2 p1 p0 r/ w a0 a1 a2 a3 0 0 scl 1 c1 p3 1 99 d7 d6 d5 d2 d1 /0 d0 /0 d4 d3 ack. by ad7997/ad7998 stop by master least significant data byte most significant data byte scl (continued) sda (continued) frame 1 serial bus address byte start by master frame 2 address pointer register 91 0 00 d10 d9 d8 0 d1 1 ack. by ad7997/ad7998 03473-0-028 f i gure 28. 2-b y te write s e quen c e
ad7997/ad7998 rev. 0 | page 26 of 32 reading da t a from the ad7997/ad7998 readin g da ta f r o m the ad7997 /ad7998 is a 1- o r 2-b y t e o p era t ion. re adin g b a ck t h e con t e n ts o f t h e ale r t s t a t us r e g i st er o r t h e c y cle t i mer r e g i s t er is a si n g le-b yt e r e ad op era t ion, as shown i n f i g u re 2 9 . this assu me s t h e p a r t ic u l ar re g i ste r addre s s has p r e v io us l y b e en s e t u p b y a sin g le-b yte wr i t e o p era t ion t o t h e addr es s p o i n t e r r e g i s t er , as s h own i n f i gur e 26. on ce t h e r e g i s t er addr es s has b e en s e t u p , a n y n u m b er o f r e ads can b e p e r f or me d f r om t h at p a r t i c u l ar re g i ste r w i t h o u t h a v i ng to w r ite to t h e a ddr ess p o in ter r e g i ster aga i n. i f a re a d f r om a d i f f e r e n t re g i ste r i s re qu i r e d , t h e rel e v a n t r e g i s t er addr es s has t o b e wr i t te n t o t h e addr es s p o in t e r r e g i s t er , a nd a g ain an y n u m b er o f r e ads f r o m t h is r e g i ster ma y t h e n b e pe rf o r m e d . re ad in g d a t a f r o m t h e co nf igur a t io n reg i st er , c o n v ersio n r e su l t re g i ste r , d a t a hi gh re g i ste r s , d a t a lo w re g i ste r s , or h y ste r e s is r e g i s t ers is a 2-b y t e o p era t io n, as s h own in f i gu r e 30. th e s a me r u les a p ply fo r a 2-b y t e r e ad as a sin g le-b y t e r e a d . w h en r e adin g da t a b a ck f r o m a r e g i s t er , fo r exa m ple t h e c o n v e r s i on re su lt re g i ste r , i f mo re t h an t w o re a d by te s are s u p p lie d , th e s a m e o r new da ta is r e ad f r o m th e ad7997/ ad7998 wi t h o u t th e n e ed t o r e addr es s t h e de vic e . this al lo ws t h e m a ste r to c o n t i n u o u sly re ad f r om a d a t a re g i ste r w i t h ou t ha vin g t o r e addr es s th e ad799 7/ad7998. sda 11 99 d7 d6 d5 d2 d1 d0 r/w a0 a1 a2 a3 0 1 scl d4 d3 0 03473-0-029 start by master ack. by ad7997/ad7998 no ack. by master stop by master frame 1 serial bus address byte frame 2 single data byte from ad7997/ad7998 f i g u re 29. r e ad ing a s i ng le b y te of d a t a f r om a s e lec t ed r e g i s t er s d a 11 9 9 alert flag chid2 d10 d9 d8 a0 a1 a2 a3 0 0 scl 1 d1 1 1 d7 d6 d5 d2 d1/0 d0/0 d4 d3 scl (continued) sda (continued) ch id1 ch id0 r/w 03473-0-030 9 start by master ack. by ad7997/ad7998 no ack. by master ack. by master stop b y master frame 1 serial bus address byte frame 2 most significant data byte from ad7997/ad7998 frame 2 most significant data byte from ad7997/ad7998 f i gur e 3 0 . rea d i n g t w o byt e s o f da t a f r om the c o n v er sion resul t regi ster
ad7997/ad7998 rev. 0 | page 27 of 32 alert/busy pin the aler t/b u s y p i n ma y be c o nf igur ed as an aler t o u t p u t o r as a b u sy o u t p ut , as sh own i n t a b l e 12. smbus alert the ad7997/ad7998 aler t o u t p u t is a n s m b u s in t e r r u p t lin e fo r de vices t h a t wa n t t o t r ade t h eir a b i l i t y t o mas t er fo r a n ext r a p i n. th e ad799 7/ad7998 is a sla v e-o n l y device tha t us es the s m b u s aler t t o sig n al th e h o s t de vice tha t i t wa n t s t o tal k . the s m b u s al er t o n t h e ad7997/ad7998 is us ed as an o u t- o f -ra n ge i n dic a to r (a limi t viol a t io n i n di c a t o r). the a l er t p i n has a n op en -dr a in co nf igur a t ion t h a t a l lo ws th e aler t o u t p u t s o f s e v e ral ad7997/ad79 98s t o be wir e d- and e d t o g e t h er wh en t h e ale r t p i n is ac ti ve lo w . d0 o f th e co nf igura t io n r e g i st er is us e d t o s e t t h e ac t i v e p o la r i ty o f t h e aler t ou t p u t . the p o wer - u p d e fa u l t is ac t i ve l o w . th e aler t f u n c t i on can b e ena b le d o r dis a b l e d b y s e t t in g d2 o f t h e co n - f i gura tio n r e g i s t er t o 1 o r 0, r e s p ec ti v e l y . t h e h o s t devi ce ca n p r oces s t h e al e r t i n t e rr u p t a n d s i m u l t a n e - ou sly ac c e ss a l l s m bu s a l e r t de v i c e s t h rou g h t h e a l e r t re sp ons e addr es s. onl y t h e de vice t h a t pu l l e d t h e aler t l o w ackn o w le dges t h e aler t r e s p o n s e addr es s ( a r a ). i f m o r e t h a n o n e de vice p u l l s t h e aler t p i n lo w , t h e hig h est p r io r i ty (lo w es t addr es s) de v i ce wi n s co m m unic a t io n r i g h ts vi a st anda r d i 2 c a r b i t r a t io n d u r i n g th e sla v e addr ess tra n sfer . the a l er t ou t p u t b e com e s ac t i v e w h e n t h e val u e in t h e co n v ersio n r e s u l t r e g i s t er exce e d s t h e v a l u e i n t h e d a t a hi g h r e g i s t er o r fal l s b e lo w t h e val u e in t h e d a t a lo w re g i ste r f o r a s e lec t e d c h a n nel . i t is r e s e t when a wr i t e op era t io n t o t h e co nf igura t io n r e g i s t er s e ts d1 t o a 1, o r wh en t h e co n v ersion re su lt re tu r n s n ls b b e lo w o r a b o v e t h e val u e st o r e d i n t h e da t a hi g h r e g i ster o r t h e d a t a lo w re g i ste r , re sp e c t i vely . n is t h e val u e in t h e h y st er esis r e g i s t er (s e e t h e l i mi t re g i s t ers s e c t io n). the a l er t ou t p u t r e q u ir es an ext e r n al p u l l -u p r e sis t o r t h a t can b e co nne c t e d t o a v o l t a g e dif f er en t f r o m v dd prov i d e d t h e m a x i - m u m v o l t a g e ra ti n g o f th e a l er t o u t p u t p i n is n o t e x ceeded . t h e v a l u e o f th e p u ll- u p r e si s t o r d e pen d s o n th e a p p l i c a t i o n , b u t s h o u ld b e as la rg e as p o s s ib le t o a v o i d exces s i v e sink c u r r en ts a t th e a l er t o u t p u t . busy w h en t h e ale r t/b u s y p i n is co nf igur ed as a b u s y o u t p u t t h e p i n is us e d t o indic a t e w h en a c o n v ersio n is t a k i n g p l ac e . th e p o la r i ty o f t h e b u s y pin is p r o g r a mme d t h r o ug h b i t d0 in t h e c o nf igura t io n reg i st er . pl a c ing the ad7997-1/ ad7998-1 int o high spee d mode h i g h sp e e d m o de co m m unic a t io n co m m e n ces a f ter t h e maste r addr es s e s al l de vices co nne c t e d t o t h e b u s w i t h t h e mas t er co de, 00001x x x , t o in dic a t e tha t a hig h s p e e d m o de tra n sf er is t o b e g i n. n o d e v i c e con n e c te d to t h e b u s is a l lo we d to ack n ow l e dge t h e hig h sp e e d mas t er co de; t h er efo r e , t h e co de is fol l o w e d b y a n o t - ack n o w le dge (s e e f i gur e 31 ). th e mas t er m u s t t h e n is s u e a r e pea t ed s t a r t f o ll o w ed b y th e devi ce a d d r e s s w i th a n r / w bi t . the s e le c t e d de vice t h e n ack n o w le dges i t s ad dr ess. a l l de vices con t in ue to o p er a t e in hig h sp e e d mo de un t i l such a t i me as t h e mast er is s u es a st o p co ndi t i on. w h e n t h e s t o p condi - t i on is issu e d , t h e de v i c e s a l l re tu r n to f a st mo d e . the addre ss selec t ( a s) pin the addr es s s e l e c t p i n on t h e ad7997/ad7998 is us ed t o s e t th e i 2 c addr es s f o r th e ad7997 /ad7998 de vice. th e a s p i n can be tied t o v dd , t o a g n d , o r l e f t f l o a t i n g . t h e s e l e c t i o n s h o u l d b e ma de as clo s e as p o ssib le to t h e as pin; a v o i d ha vi n g lo n g tra c k s i n tr od ucin g e x tra ca pa ci t a n c e o n t o t h e p i n . t h i s i s im p o r t an t fo r t h e f l o a t s e le c t ion, as t h e a s p i n has t o cha r ge t o a mid p o i n t a f t e r t h e st a r t b i t d u r i n g t h e f i rst address b y t e . e x t r a ca p a c i t a n c e on t h e a s pin i n cr e a s e s t h e t i m e t a k e n t o cha r g e t o t h e m i dp oi n t a n d m a y c a u s e a n i n c o r r e c t d e c i s i on on t h e d e v i c e addr es s. w h en t h e a s p i n is lef t f l o a tin g , the ad7997/ad7998 ca n w o rk wi t h a ca p a ci ti v e lo ad u p t o 40 pf . sda ack. by ad7997/ad7998 start by master hs mode master code serial bus address byte nack 19 1 9 0 1 a2 a1 a0 x x 1 0 0 0 scl 0 0 a3 x sr fast mode high speed mode 03473-0-031 f i gure 3 1 . p l a c i n g t h e p a r t i n to hi gh s p eed m o de
ad7997/ad7998 rev. 0 | page 28 of 32 modes of opera tion w h en su p p lies a r e f i rs t a p p l ie d t o th e ad7997 /ad7998, the ad c p o w e rs up in sle e p m o de a nd n o r m a l ly r e ma in s i n t h is s h u t do w n s t a t e w h i l e n o t con v e r t i n g . th er e a r e t h r e e m e t h o d s o f ini t ia tin g a c o n v ersio n on t h e ad7997 /ad7 998. mode 1u s ing the c o nv st pi n a co n versio n can b e ini t ia t e d on the ad7997/ad7998 b y pu l s i n g t h e co n v s t sig n al . the con v ersio n clo c k fo r t h e p a r t is in t e r n a l ly genera t e d s o n o exter n a l clo c k is r e q u ir e d , excep t w h en r e adin g f r o m o r wr i t i n g to t h e s e r i al p o r t . on t h e r i sin g ed g e o f co n v s t , th e ad7997/ad7998 b e g i n s t o p o w e r u p (s ee po i n t a in f i g u r e 3 2 ) . t h e po w e r - u p tim e f r o m s h u t d o wn m o d e f o r th e ad7997 /ad7998 is a p p r o x ima t e l y 1 s; th e co n v s t sig n al m u s t r e ma in hig h f o r 1 s f o r th e p a r t t o p o w e r u p f u l l y . co n v s t ca n be b r o u gh t lo w a f t e r th i s ti m e . t h i s po w e r - u p t i me als o in cl udes t h e ac q u isi t ion t i m e o f t h e a d c. th e fal l ing ed g e o f th e co n v s t signa l places t h e t r ack-and- h o ld in t o h o ld m o d e ; a con v ers i o n is a l s o ini t i a t e d a t t h is p o in t (p o i n t b in f i gur e 32). w h en the con v ersio n is co m p let e , a p p r o x ima t e l y 2 s la ter , th e p a r t r e t u r n s t o s h u t do wn (p o i n t c in f i gur e 32) a n d r e m a in s th er e un til t h e n e xt ri si n g ed g e o f co n v s t . t h e m a s t e r ca n t h en r e a d th e ad c t o o b ta in th e co n v e r si o n r e s u l t . the addr es s p o i n t e r r e g i s t er m u s t b e p o i n t i n g to t h e con v ersion re su lt re g i ste r i n ord e r to re a d b a ck t h e c o n v e r s i on re su lt . if t h e co n v s t p u ls e do es n o t r e main hi g h fo r m o r e t han 1 s, th e fal l in g edge o f co n v s t s t ill i n i t ia t e s a co n v e r si o n b u t th e r e s u l t is in valid be ca us e t h e ad7997/ad7998 ar e n o t f u l l y p o w e r e d-u p w h en t h e con v ersio n t a k e s place . t o ma i n t a in t h e p e r f o r ma n c e o f th e ad7997 /ad7998 in this mo de i t is r e co mme n d e d t h a t t h e i 2 c b u s is q u iet w h e n a c o n v ersio n is taki n g pla c e . the c y cle t i m e r r e g i s t er an d bi ts c4 t o c1 in t h e addr es s p o in ter r e g i s t er sh o u ld co n t a i n al l 0s w h en o p era t in g t h e ad7997 / ad7998 in this m o de . th e co n v s t p i n s h o u ld b e tied l o w f o r a l l ot he r mo d e s of op e r a t i o n . t o s e l e c t an an a l o g i n put ch an n e l for c o n v e r s i on i n t h i s mo d e , t h e us er m u st w r i t e t o t h e co nf i g ura t io n r e g i st e r a n d s e le c t t h e co r r es p o n d in g cha n n e l f o r co n v ersio n . t o s e t u p a s e q u en ce o f ch an nel s to b e c o n v e r te d w i t h e a ch co n v s t pu l s e, s e t t h e co r r esp o n d in g cha n n e l b i ts in t h e conf igura t ion r e g i st er (s e e t a b l e 11). on ce a con v ersi o n is co m p le t e , t h e mas t er ca n addr es s t h e ad7997/ad79 98 t o r e ad the c o n v ersio n r e s u l t . i f f u r t h e r co n v ersio n s a r e r e q u ir e d , t h e sc l line can b e t a k e n hig h w h i l e th e co n v s t s i g n a l i s pu l s e d ag ai n ; t h e n an a d d i t i on a l 1 8 s c l p u ls es a r e r e q u ir e d t o r e ad t h e co n v ersio n r e s u l t . w h en o p era t ing th e ad7997 -1/ad7998 -1 in m o de 1 an d r e adin g a f t e r con v ersio n wi th a 3.4 mh z f sc l , t h e a d c s c a n ac hieve a typ i ca l thr o ug h p u t ra te o f u p t o 121 ks ps. 11 9 sca 9 s 7-bit address ra first data byte (msbs) a second data byte (lsbs) 9 p sda t power-up b a c t convert 03473-0-032 convst a f i g u re 32. m o d e 1 o p er at ion
ad7997/ad7998 rev. 0 | page 29 of 32 mode 2 C command mode this mode allows a conversion to be automatically initiated any time a write operation occurs. in order to use this mode, the command bits c4 to c1 in the address pointer byte shown in table 7 must b e pro g r amme d. to select a single analog input for conversion in this mode, the user must set bits c4 to c1 of the address pointer byte to indicate which channel to convert on (see table 26). when all four command bits are 0, this mode is not in use. to select a sequence of channels for conversion in this mode, first select the channels to be included in the sequence by setting the channel bits in the configuration register. next, set the command bits in the address pointer byte to 0111. with the command bits of the address pointer byte set to 0111, the adc knows to look in the configuration register for the sequence of channels to be converted. the adc starts converting on the lowest channel in the sequence and then the next lowest until all the channels in the sequence are converted. the adc stops converting the sequence when it receives a stop bit. figure 29 illustrates a 2-byte read operation from the conversion result register. this operation is preceded typically by a write to the address pointer register so that the following read accesses the desired register, in this case the conversion result register (see figure 26). if command bits c4 to c1 are set when the contents of the address pointer register are being loaded, the ad7997/ad7998 begins to power up and convert upon the selected channel(s). power-up begins on the fifth scl falling edge of the address point byte, (see point a in figure 33). table 26 shows the channel selection in this mode via command bits c4 to c1 in the address pointer register. the wake-up, acquisition, and conversion times combined should take approximately 3 s. following the write operation, the ad7997/ad7998 must be addressed again to indicate that a read operation is required. the read then takes place from the conversion result register. this read accesses the conversion result from the channel selected via the command bits. if command bits c4 to c1 were set to 0111, and bits d4 and d5 were set in the configuration register, a 4-byte read would be necessary. the first read accesses the data from the conversion on v in 1. while this read takes place, a conversion occurs on v in 2. the second read accesses this data from v in 2. figure 34 illustrates how this mode operates; the user would first have written to the configuration register to select the sequence of channels to be converted before write addressing the part with the command bits set to 0111. when operating the ad7997-1/ad7998-1 in mode 2 with a high speed mode, 3.4 mhz scl, the conversion may not be complete before the master tries to read the conversion result. if this is the case, the ad7997-1/ad7998-1 holds the scl line low during the ack clock after the read address, until the con- version is complete. when the conversion is complete, the ad7997-1/ad7998-1 releases the scl line and the master can then read the conversion result. after the conversion is initiated by setting the command bits in the address pointer byte, if the ad7997/ad7998 receives a stop or nack from the master, the ad7997/ad7998 stops converting. table 26. address pointer byte c4 c3 c2 c1 p3 p2 p1 p0 mode 2, convert on comments 0 0 0 0 0 0 0 0 not selected 1 0 0 0 0 0 0 0 v in 1 1 0 0 1 0 0 0 0 v in 2 1 0 1 0 0 0 0 0 v in 3 1 0 1 1 0 0 0 0 v in 4 1 1 0 0 0 0 0 0 v in 5 1 1 0 1 0 0 0 0 v in 6 1 1 1 0 0 0 0 0 v in 7 1 1 1 1 0 0 0 0 v in 8 0 1 1 1 0 0 0 0 sequence of channels selected in the configuration register, bits d11 to d4. with the pointer bits p3Cp0 set to all 0s, the next read accesses the results of the conversion result register.
ad7997/ad7998 rev. 0 | page 30 of 32 9 11 a 9 s wa a sr ra a second data byte (lsbs) first data byte (msbs) command/address point byte 7-bit address 7-bit address a sda 11 9 scl sda scl 9 9 sr/p 8 ack by ad7997/ad7998 ack by ad7997/ad7998 ack by master nack by master ack by ad7997/ad7998 03473-0-033 f i g u re 33. m o d e 2 o p er at ion 9 11 scl 9 s 7-bit address wa command/address point byte a s d a first data byte (msbs) a second data byte (lsbs) first data byte (msbs) second data byte (lsbs) a sr 7-bit address ra sda 9 9 1 1 scl 9 8 ack by ad7997/ad7998 ack by ad7997/ad7998 ack by master ack by master ack by master ack by ad7997/ad7998 a 9 9 result from ch1 result from ch2 a/a 03473-0-034 f i gure 34. mod e 2 s e quence o p e r at ion mode 3 a u t o ma tic c y cle interv al mode an a u to ma t i c c o n v ersio n c y cle ca n b e s e le c t e d a nd enab le d b y wr i t i n g a val u e to t h e c y cle t i m e r r e g i s t er . a co n v ersio n c y cle in t e r v al c a n be s e t u p o n t h e ad7997/ad7998 b y p r og ra mmin g t h e r e l e van t b i ts in t h e 8- b i t c y cle t i m e r r e g i s t er , as de co de d in t a b l e 24. onl y t h e 3 l s bs a r e us e d t o s e le c t t h e c y cle in t e r v al; th e 5 ms b s sh ou ld co n t ain 0s. w h en t h e 3 l s bs o f th e r e g i s t er a r e p r o g r a mm e d w i t h an y co nf i g ur a t io n o t h e r t h a n a l l 0s, a co n v ersio n t a k e s place e v er y x m s ; t h e c y cle in ter v al , x, dep e n d s on t h e co nf igura t io n of t h es e t h r e e b i t s in t h e c y cle t i mer r e g i s t er . th er e a r e s e v e n dif f er en t c y cle t i m e in ter v als t o ch o o s e f r o m , as s h own i n t a b l e 24. on ce t h e con v ersio n has t a k e n pl ace, t h e p a r t p o w e rs do w n a g a i n un t i l t h e n e x t con v er - sio n o c c u rs. t o exi t t h is m o de of o p era t io n, t h e us er m u s t p r og ra m t h e 3 l s bs o f t h e c y cle t i mer r e g i s t er t o co n t a i n al l 0s. t o s e le c t a chann e l(s) fo r o p era t io n i n t h e c y cle m o de , s e t t h e co r r es p o n d in g cha n n e l b i t(s), d11 t o d4, o f th e co nf igura t io n r e g i st er . i f m o r e t h a n on e channe l b i t is s e t in t h e co nf igura t ion r e gi s t e r , th e a d c a u t o m a ticall y c y c l e s th r o ugh th e c h a n n e l seq u en ce sta r ti n g wi th t h e lo w e s t c h a n n e l a n d w o r k i n g i t s wa y u p th r o ugh th e seq u en ce . on ce th e s e q u en ce i s co m p le t e , t h e a d c s t ar t s c o n v e r t i ng on t h e l o we st ch an nel a g ai n , c o n t i n u i n g t o loo p th r o ugh th e se q u en ce un til t h e c y c l e tim e r r e gi s t e r co n t e n ts a r e s e t t o a l l 0s. this mo de is us ef u l fo r m o ni t o r i n g sig n als, s u ch as b a t t er y v o l t a g e a nd t e m p er a t ure , aler t i n g o n l y w h en t h e limi ts a r e viol a t e d .
ad7997/ad7998 rev. 0 | page 31 of 32 outline dimensions 20 1 11 10 6.40 bsc 4.50 4.40 4.30 pin 1 6.60 6.50 6.40 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 compliant to jedec standards mo-153ac coplanarity 0.10 f i gure 35. 2 0 -l ead thin shr i nk s m a l l o u tline p a ckage [ t ssop ] (ru - 20) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model 1 temperature r a nge linearity error 2 (max) package option package descri ption ad7997bru-0 C40c to +85c 0.5 lsb ru-20 tssop ad7997bru-0r eel C40c to +85c 0.5 lsb ru-20 tssop ad7997bruz-0 3 C40c to +85c 0.5 lsb ru-20 tssop ad7997bruz-0 r eel 3 C40c to +85c 0.5 lsb ru-20 tssop ad7997bru-1 C40c to +85c 0.5 lsb ru-20 tssop ad7997bru-1r eel C40c to +85c 0.5 lsb ru-20 tssop ad7997bruz-1 3 C40c to +85c 0.5 lsb ru-20 tssop ad7997bruz-1 r eel 3 C40c to +85c 0.5 lsb ru-20 tssop ad7998bru-0 C40c to +85c 1 lsb ru-20 tssop ad7998bru-0r eel C40c to +85c 1 lsb ru-20 tssop ad7998bruz-0 3 C40c to +85c 1 lsb ru-20 tssop ad7998bruz-0 r eel 3 C40c to +85c 1 lsb ru-20 tssop ad7998bru-1 C40c to +85c 1 lsb ru-20 tssop ad7998bru-1r eel C40c to +85c 1 lsb ru-20 tssop ad7998bruz-1 3 C40c to +85c 1 lsb ru-20 tssop ad7998bruz-1 r eel 3 C40c to +85c 1 lsb ru-20 tssop eval-ad7997c b standalone evaluation board eval-ad7998c b standalone evaluation board 1 the ad7997-0/ad 7998-0 support standard and fast i 2 c i nterface modes. th e ad7997-1/ad7998-1 suppo rt standar d , fast, and high sp eed i 2 c i n t e rfa c e m o de s. 2 linearity error here re fer s to inte gral n o nl ine a rity. 3 z = pb-free part. rel a ted p a rt s in i 2 c- c o mp a t ible adc produ c t f a mil y part number resolution number of input channels package ad7994 1 2 4 1 6 t s s o p ad7993 1 0 4 1 6 t s s o p ad7992 1 2 2 1 0 m s o p
ad7997/ad7998 rev. 0 | page 32 of 32 notes purch a se of li c e n s e d i 2 c com p on en t s o f an a l og d e vi ces or on e of i t s subli c en s e d as soci a t ed c o m p a n i e s con v eys a li cen s e for t h e purch a ser un der t h e ph i li p s i 2 c p a te nt rights to us e the s e co mpo n e nts in an i 2 c sy st em , provi d e d t h a t t h e syst em c o n f orm s t o t h e i 2 c stand a rd speci f ication as d e f i ned by phil ips . ? 2004 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d ema r ks are the prop erty of their respective owners . d03473C0C 9/04(0)

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